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Memory barrier
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#	Item
61	Fence-Free Work Stealing on Bounded TSO Processors Adam Morrison ∗ Yehuda Afek Computer Science Department Add to Reading List Source URL: www.cs.technion.ac.il Language: English Computer hardware Abstract data types Concurrency control Circular buffer Memory barrier Double-ended queue Parallel Extensions Queue Algorithm Computing Computer memory Computer architecture
62	Automatic Nonblocking Communication for Partitioned Global Address Space Programs Wei-Yu Chen1,2 Dan Bonachea1,2 Costin Iancu2 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2008-06-09 18:39:59 Concurrent computing Parallel computing Concurrency control Unified Parallel C Prefetch buffer Remote direct memory access Memory barrier Monitor Cache Computing Computer memory Software engineering
63	Atomic Instructions in Java David Hovemeyer, William Pugh, and Jaime Spacco Dept. of Computer Science, University of Maryland, College Park, MDUSA {daveho,pugh,jspacco}@cs.umd.edu Abstract. Atomic instructions at Add to Reading List Source URL: faculty.ycp.edu Language: English - Date: 2014-08-22 12:24:21 Concurrency Compare-and-swap Linearizability Double compare-and-swap Lock Load-link/store-conditional Non-blocking algorithm Memory barrier Monitor Concurrency control Computing Computer architecture
64	Location-Based Memory Fences Edya Ladan-Mozes I-Ting Angelina Lee Dmitry Vyukov∗ Add to Reading List Source URL: www.cse.wustl.edu Language: English - Date: 2014-08-27 02:16:24 Central processing unit Computer memory Concurrency control Microprocessors Memory barrier CPU cache Parallel computing Linearizability Microarchitecture Computer architecture Computing Computer hardware
65	Barriers: Friend or Foe? Steve Blackburn Tony Hosking Add to Reading List Source URL: researchweb.watson.ibm.com Language: English - Date: 2005-02-16 12:34:05 Jikes RVM MOV Advanced Micro Devices Memory barrier CPUID Computer architecture Computing X86
66	Techniques for Low Overhead Fences and Sequential Consistency Violation Recording Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-12-18 00:20:34 Memory barrier Parallel computing Computing Structure Fences Computer memory Electric fence
67	Optimizing OpenCL for NVIDIA GPUs Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:09:19 Graphics hardware Video cards Parallel computing Nvidia OpenCL CUDA Graphics processing unit Memory barrier Comparison of Nvidia graphics processing units Computer hardware Computing GPGPU
68	Microsoft Word[removed]Title template 3b-blank20100506.docx Add to Reading List Source URL: www.hpl.hp.com Language: English - Date: 2012-12-07 12:02:39 Computer architecture CPU cache Write-combining Cache X86-64 Memory barrier X86 Memory ordering Dynamic random-access memory Computer memory Computer hardware Computing
69	Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications Jose´ F. Mart´ınezy and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign Urb Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2002-07-31 19:58:04 Concurrent computing Lock Non-blocking algorithm Critical section Memory barrier Barrier Parallel computing OpenMP Deadlock Concurrency control Computing Computer programming
70	Asymmetric Memory Fences: Optimizing Both Performance and Implementability ∗ Yuelu Duan, Nima Honarmand, † and Josep Torrellas University of Illinois at Urbana-Champaign {duan11,torrella}@illinois.edu nhonarmand@cs.s Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2015-01-19 15:13:18 Computer programming Computer memory Memory barrier Deadlock Double-checked locking Parallel computing Software transactional memory Cilk Eventing Computing Software engineering Concurrency control